(1) Field of the Invention
The present invention is in the field of memory access; more specifically, the present invention is related to a method and apparatus for accelerated graphics port (AGP) device read and central processing unit (CPU) write coherency.
(2) Related Art
Computer systems typically have a graphics device for processing graphics data for display on a display device. An accelerated graphics port (AGP) device (also referred herein as a graphics device) can request expedite priority in accessing a system memory over other devices including the processor. When a processor attempts to perform a write to the system memory for use by a graphics device, the graphics device responds by initiating a read to the system memory. The read is initiated while the processor write data remains in an intermediate buffer prior to being posted to the system memory. If the graphics device is able to read around the previously posted write data, a data coherency problem is created.
The prior art attempts to solve the data coherency problem by snoop stalling the processor initiated write to the graphics device. A snoop phase in general are used to maintain data coherency between the processor's internal cache and the system memory. Each cycle initiated by the processor has a snoop phase. Wait states may be inserted by a device in this phase (referred to as a snoop stall) if the device is not able to process the cycle immediately.
A disadvantage of the prior art is that the processor will not issue additional cycles until after the completion of the snoop phase. The prior art therefore leads to a performance penalty, since the processor bandwidth to the system memory is negatively affected.
It is therefore desirable to provide a method and an apparatus to ensure data coherency between graphics device reads and processor writes while minimizing the effect on the processor bandwidth to the system memory.